This invention relates in general to voltage translators, and more particularly, to an ECL to TTL voltage translator having a clamping circuit for limiting the low level TTL output signal to a predetermined value.
It is well known that many of today's complex electronic systems mix and match integrated circuits of different logic families to accomplish a series of interrelated functions. In one example, signals produced in the ECL (emitter coupled logic) family are converted to levels compatible with the TTL (transistor-transistor logic) family by a voltage translator circuit for further processing. The output stage of the conventional ECL to TTL voltage translator typically includes upper and lower bipolar transistors alternately conducting and serially coupled between a power supply conductor operating at a positive potential such as V.sub.CC and a ground potential terminal. The output is provided at the interconnection of the transistor pair. The upper transistor in the output stage pulls the output terminal toward V.sub.CC for providing a high TTL output signal, while the lower transistor draws the output terminal toward ground potential for providing a low TTL compatible output signal. It is important to clamp the low output voltage (V.sub.OL) within a predetermined narrow window of operation, otherwise if the V.sub.OL signal became too high it would exceed the generally accepted industry standard for a low TTL output signal (&lt; 500 millivolts), or if the output voltage became too low, the collector-base junction of the lower transistor could become strongly forward biased, saturating the transistor and developing excessive charge in the base region thereby slowing its switching rate to an unacceptable value.
In conventional practice, a Schottky diode is coupled between the collector and base of the lower transistor in the TTL output stage for clamping the V.sub.OL output signal to approximately 300-500 millivolts. While the Schottky diode behaves satisfactorily as a clamping means, the manufacturing processes to implement the Schottky diode especially in more recent semiconductor technologies, requires several complex and expensive steps including an extra masking step to form the Schottky diode and its contacts. Although it is necessary to clamp the V.sub.OL output signal for the reasons advanced above, it is also desirable to provide such a feature without the expense and complexity imposed by the traditional Schottky diode.
Another significant problem with the conventional TTL output stage relates to the phasing of the control signals applied at the bases of the upper and lower transistors and the associated charge and discharge rates thereof, wherein it is possible for both transistors to conduct simultaneously at the transition of the output logic state creating a short circuit current therethrough which induces spikes in the power supply lines thus creating excessive system noise and peak power. In the prior art, a phase splitter transistor is typically used for alternately enabling the upper and lower transistors in the output stage. This single point of control is susceptible to race conditions taking into account the charge and discharge rates whereby the upper and lower transistors may jointly conduct between the power supply conductors for a short period of time at the transitions of the output logic state. Preferably, the control circuitry for the output stage should insure that the active transistor is completely off before the opposite one is turned on, thus avoiding the short circuit current.
Furthermore, the low level output signal of the conventional voltage translator is often sensitive to temperature variation. The V.sub.OL output signal is typically determined by the base-emitter junction potential of the lower transistor less the voltage across the Schottky clamp. The P-N junctions of the lower transistor and the Schottky diode are exponential functions of temperature as seen in the well known diode equation, V.sub.d =(kT/q) ln (I.sub.d /I.sub.s), where "V.sub.d " is the potential across the diode, "I.sub.d " is the current through the diode, "I.sub.s " is the diode saturation current, "k" is Boltzman's constant, "T" is absolute temperature and "q" is the electron charge. Hence, the V.sub.OL output signal is known to fluctuate with temperature by as much as 200-300 millivolts from 0.degree. C. to 125.degree. C. which is unacceptable in some applications and undesirable in most others.
Hence, there is a need for an improved ECL to TTL translator which limits the low output voltage to a predetermined value independent of temperature and without the use of a Schottky diode clamp, while insuring that the upper and lower transistors in the output stage do not conduct simultaneously.